VLSI ALU Unit

Project Description:

A digital VLSI project to design a 16-bit ALU (multiplier, adder, subtractor) unit. This unit takes in two 16-bit operands that are first stored in a 64x16 bit SRAM (so there are 64 potential operands). Depending on the desired operation, the ALU will perform multiplication, addition, or subtraction and store the result in a 32 bit D-Flip Flop structure. The result is then stored in a 62x32 bit SRAM, giving 64 locations for answer storage. The project was done with a partner, with the design and layout done in Cadence Virtuoso. The circuit was analyzed for worse case critical paths and optimized for product, area, and delay. The Booth Multiplier architecture was used with a Carry Increment Adder architecture. The circuit was also optimized using dynamic logic, power optimization techniques, and architectural optimizations in the ALU, memory and D-flip flops.

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Responsibilities:

• Design and layout 16-bit ALU, buffer units (demux) and SRAM memory to build ALU unit. 

• Optimize architectures and layout in Cadence Virtuoso to generate lowest power, area, and delay product.

• Run exhaustive simulations to find worst case delay and maximum achievable clock frequency of 50 MHz.