VLSI MAC Unit

Apr 2021- May 2021

Project Description:

A digital VLSI project to design a Multiply-Accumulator Circuit (MAC) unit. This unit takes a two 6 bit inputs and multiplies them to store in an 16-bit DFF register with adder accumulation. The project was done with a partner, with the design and layout done in Cadence Virtuoso. The circuit was also analyzed for worse case delay and critical paths. The Wallace Tree architecture was used for the multiplier and a Carry Increment Adder architecture was used for the adder.

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Responsibilities:

• Design and layout 6-bit multiplier, 16-bit adder, 16-bit D-flip flop, buffer units and load units to build MAC unit. 

• Optimize architectures and layout in Cadence Virtuoso to generate lowest area and delay product.

• Run exhaustive simulations to find worst case delay, critical paths, and maximum achievable clock frequency of 277 MHz for unit.