Asynchronous SNN Accelerator

Project Description:

An asynchronous Spiking Neural Network NoC architecture was built to take in 5x5 input spike maps and a 3x3 filter weight map to compute membrane potentials and threshold spikes. The design was built in SystemVerilogCSP and simulated/tested in collaboration with 2 other group members.

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Responsibilities:

• Design SNN NoC architecture to maximize throughput, latency, computation utilization, area, and energy.

• Simulated all modules and submodules in SystemVerilog to achieve functional performance and present results to class.