Verilog RTL Processor and NoC

Project Description:

A digital design project (worked with 1 other person) to write RTL code to synthesize a 4 stage processor and 4 node ring NoC. All submodules were written and tested through testbenches or Python simulators (ALU, register file, decoder, pipeline stages, router, arbiters, etc). The final synthesized design passed automatic place and route and runs off of a 30 ns clock.

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Responsibilities:

• Design cardinal processor and ring NoC to optimize performance in area, power, and speed.

• Test all modules and submodules through Verilog and Python simulators to verify functionality.